1. Field
Example embodiments relate to structure of transformers, for example, a symmetric transformer, a balanced-unbalanced transformer (balun) and an integrated circuit including the symmetric transformer.
2. Description of the Related Art
Requirement for low cost monolithic integrated circuits are accelerating techniques of integrating more elements in a single chip. A system-on-chip (SoC) includes a system that has a variety of electrical components formed on a printed circuit board (PCB) or a semiconductor substrate.
A passive element, for example, a transformer, integrated in the SoC may have a relatively poor performance than an off-chip transformer.
The transformer may include two inductors, for example, two coils that are disposed such that they may be coupled electromagnetically. The transformer may transfer a signal from an input coil to an output coil. A performance of a transformer is based on several factors, including, but not limited to, inductance of the coils, a quality factor (Q-factor), a magnetic coupling ratio, overall symmetry of the transformer structure. A high performance transformer has a higher inductance value, a higher Q-factor, a higher magnetic coupling ratio and high overall symmetry.
An on-chip transformer may be realized by two separate coils formed and suitably disposed on a semiconductor substrate. Passive elements such as inductors and transformers may be formed in upper layers on the semiconductor substrate after forming wires. The on-chip transformer may be required to occupy a smaller area to achieve an increased degree of integration, but characteristics of such an on-chip transformer, for example, a Q-factor and a magnetic coupling ratio maybe affected (for example, reduced) as a size of the transformer is reduced. The on-chip transformer may also have a relatively low performance as compared to the off-chip transformer, because a thickness of a metal layer forming the on-chip transformer and losses in the semiconductor substrate may be relatively higher. Under such integration conditions, optimization of the on-chip transformer structure may be required for an increased performance of the on-chip transformer.
The conventional on-chip transformer occupies a larger area, however provides a smaller value of inductance. A primary coil and a secondary coil may be disposed vertically with respect to each other to decrease horizontal occupation area. In this case, however, symmetry of the transformer may be reduced due to asymmetric parasitic capacitances between an upper coil and a lower coil. If a higher number of metal layers are used to obtain desired characteristics, a distance between the transformer and the semiconductor substrate may be decreased and thus the losses into the semiconductor substrate may be increased.